18 May, 2010 § 1 Comment
This blog post was co-authored by Brendan Grebur and Jared Wein.
As a follow up from the previous post on TLB misses, I’d like to cover a special case of TLB misses.
At boot time there is a “chicken-and-egg” dilemma where the TLB is empty yet TLB values are needed immediately.
How does a computer handle this? First to make some assumptions:
- Linux Kernel
- Hardware-managed TLB
The x86 chips boot up in Real Mode with a very limited memory space and the MMU disabled. The Linux kernel is uncompressed and loaded into low-memory by the boot loader. Assembly code initializes a page directory for the initial kernel process, sets the CR3 register, then enables the PG bit in CR0 to effectively enable the MMU and begin addressing in Protected Mode. Since this area is kernel memory, the virtual address will be identical to the physical address, as kernel memory is never swapped out. The init process begins running C code and making memory references to initialize the rest of the kernel. TLB misses occur, but resolve themselves as the MMU walks the page directory previously set up for the kernel process.
17 May, 2010 § Leave a comment
This blog post was co-authored by Jared Wein and Brendan Grebur.
A Hardware-controlled TLB.
A x86(32-bit) machine using 4kB memory pages.
The CR3 register on the x86 chip will be loaded with the General Page Directory physical address for the current running process.
A General Page Directory (GPD) contains 1024, 4-byte entries of physical addresses to Internal Page Tables (IPT). The Internal Page Tables themselves consist of 1024, 4-byte entries, which contain the physical page number.
This two-level Page Table scheme translates:
The upper 10 bits (31-22) in a Virtual Address (VA) as an offset into the General Page Directory.
The next 10 bits (21-12) are translated as an offset into the Internal Page Table pointed at by the General Page Directory’s entry.
The entry in the Internal Page Table contains the physical page number the VA refers to and the lower 12 bits (11-0) serve as the byte offset into this physical page.
As the correct PTE has been loaded into the TLB, the faulting instruction is restarted, resulting in a TLB hit.